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#	Item
501	A PROCESSOR ARCHITECTURE Mark R. Thistle Institute for DefenseAnalyses SupercomputingResearchCenter Lanham,Maryland 20706 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2003-06-11 14:31:52 Central processing unit Instruction set Microarchitecture Instruction cycle Addressing mode Parallel computing Superscalar Transport triggered architecture Computer architecture Computer engineering Computer hardware
502	Microsoft Word - SSD1921-application_note-register_table-1.0.doc Add to Reading List Source URL: www.solomon-systech.com Language: English - Date: 2011-05-27 04:56:57 Central processing unit Control register Microcontrollers TI MSP430 Computer architecture Computing Instruction set architectures
503	GridOn Correlated Availability In Internet Distributed Systems Derrick Kondo1, Artur Andrzejak2, David P. Anderson3 Add to Reading List Source URL: mescal.imag.fr Language: English - Date: 2009-03-28 10:07:28 Parallel computing Distributed computing architecture Middleware Volunteer computing Berkeley Open Infrastructure for Network Computing Computer cluster American Viticultural Area Central processing unit SETI@home Computing Concurrent computing Software
504	F LUSH +R ELOAD: a High Resolution, Low Noise, L3 Cache Side-Channel Attack Yuval Yarom Katrina Falkner The University of Adelaide Add to Reading List Source URL: eprint.iacr.org Language: English - Date: 2014-07-04 21:30:09 Computer architecture Cache CPU cache Computing Computer data storage CPUID Acumem SlowSpotter AMD 10h Computer memory Computer hardware Central processing unit
505	Hybrid Analytical-Statistical Modeling for Efficiently Exploring Architecture and Workload Design Spaces Lieven Eeckhout Koen De Bosschere Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:47:52 Computing Computer memory CPU cache Cache Microprocessors Branch predictor Microarchitecture Performance prediction Computer hardware Computer architecture Central processing unit
506	Implementing an Instruction Set David E. Culler CS61CL Oct 28, 2009 Lecture 9 Add to Reading List Source URL: inst.eecs.berkeley.edu Language: English - Date: 2009-10-28 23:04:23 Central processing unit Digital electronics Electronic design Datapath Register-transfer level Flip-flop Electronic engineering Electronic design automation Electronics
507	Changes to vector_execution_policy \| N4060 Pablo Halpern, Intel Corp Add to Reading List Source URL: www.open-std.org Language: English - Date: 2014-06-20 02:01:40 Compiler optimizations Vectorization SIMD AltiVec Central processing unit Task parallelism Sequence container Vector Stream processing Concurrent computing Computing Parallel computing
508	HIMA: A Hypervisor-Based Integrity Measurement Agent Ahmed M. Azab, Peng Ning, Emre C. Sezer North Carolina State University {amazab, pning, ecsezer}@ncsu.edu Add to Reading List Source URL: discovery.csc.ncsu.edu Language: English - Date: 2011-11-09 13:25:58 Virtual machines Programming language implementation Hyper-V Kernel Hypervisor Ring Rootkit Xen Memory management unit System software Software Central processing unit
509	Outline • Why Take CS252? • Fundamental Abstractions & Concepts CS252 Graduate Computer Architecture Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2003-06-11 14:31:47 Central processing unit Classes of computers Clock signal Cycles per instruction Classic RISC pipeline Instruction pipeline Microarchitecture Instruction set CPU cache Computer architecture Computer hardware Computer engineering
510	Counting Dependence Predictors Undergraduate Honors Thesis Franziska Roesner Department of Computer Sciences The University of Texas at Austin Add to Reading List Source URL: www.franziroesner.com Language: English - Date: 2009-10-21 14:03:49 Memory dependence prediction Memory disambiguation CPU cache Alpha 21264 Microarchitecture Structural load Central processing unit Branch predictor Computer architecture Computer engineering Computer hardware

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